fix: some file didn't have the svn:eol-style native yet
This commit is contained in:
erwin.coumans
298
Extras/software_cache/cache/include/defs.h
vendored
298
Extras/software_cache/cache/include/defs.h
vendored
@@ -1,149 +1,149 @@
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/* --------------------------------------------------------------- */
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/* PLEASE DO NOT MODIFY THIS SECTION */
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/* This prolog section is automatically generated. */
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/* */
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/* (C) Copyright 2001,2006, */
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/* International Business Machines Corporation, */
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/* */
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/* All Rights Reserved. */
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/* --------------------------------------------------------------- */
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/* PROLOG END TAG zYx */
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/* spe_cache_defs.h
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*
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* Copyright (C) 2005 IBM Corp.
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*
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* Internal definitions for software managed cache.
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*/
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#ifndef __SPE_CACHE_DEFS_H__
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#define __SPE_CACHE_DEFS_H__
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/**
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** Defn's for number of cache sets.
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** Default is 64 sets.
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*/
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#if (SPE_CACHE_NSETS==1024)
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#define SPE_CACHE_NSETS_SHIFT 10
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#elif (SPE_CACHE_NSETS==512)
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#define SPE_CACHE_NSETS_SHIFT 9
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#elif (SPE_CACHE_NSETS==256)
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#define SPE_CACHE_NSETS_SHIFT 8
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#elif (SPE_CACHE_NSETS==128)
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#define SPE_CACHE_NSETS_SHIFT 7
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#elif (SPE_CACHE_NSETS==64)
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#define SPE_CACHE_NSETS_SHIFT 6
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#elif (SPE_CACHE_NSETS==32)
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#define SPE_CACHE_NSETS_SHIFT 5
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#elif (SPE_CACHE_NSETS==16)
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#define SPE_CACHE_NSETS_SHIFT 4
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#elif (SPE_CACHE_NSETS==8)
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#define SPE_CACHE_NSETS_SHIFT 3
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#elif (SPE_CACHE_NSETS==4)
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#define SPE_CACHE_NSETS_SHIFT 2
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#elif (SPE_CACHE_NSETS==2)
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#define SPE_CACHE_NSETS_SHIFT 1
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#else
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#undef SPE_CACHE_NSETS
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#define SPE_CACHE_NSETS 64
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#define SPE_CACHE_NSETS_SHIFT 6
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#endif
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/**
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** Defn's for cachline size (bytes).
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** Default is 128 bytes.
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*/
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#if (SPE_CACHELINE_SIZE==512)
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#define SPE_CACHELINE_SHIFT 9
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#elif (SPE_CACHELINE_SIZE==256)
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#define SPE_CACHELINE_SHIFT 8
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#elif (SPE_CACHELINE_SIZE==128)
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#define SPE_CACHELINE_SHIFT 7
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#elif (SPE_CACHELINE_SIZE==64)
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#define SPE_CACHELINE_SHIFT 6
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#elif (SPE_CACHELINE_SIZE==32)
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#define SPE_CACHELINE_SHIFT 5
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#else
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#undef SPE_CACHELINE_SIZE
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#define SPE_CACHELINE_SIZE 128
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#define SPE_CACHELINE_SHIFT 7
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#endif
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/**
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** Defn's derived from above settings.
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*/
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#define SPE_CACHE_NSETS_MASK (SPE_CACHE_NSETS - 1)
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#define SPE_CACHELINE_MASK (SPE_CACHELINE_SIZE - 1)
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/**
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** Defn's for managing cacheline state.
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*/
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#define SPE_CACHELINE_DIRTY 0x1
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#define SPE_CACHELINE_LOCKED 0x2
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#define SPE_CACHELINE_STATE_MASK (SPE_CACHELINE_DIRTY | SPE_CACHELINE_LOCKED)
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#ifdef _XLC
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/**
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* FIXME: For now disable manual branch hints
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* on XLC due to performance degradation.
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*/
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#ifndef likely
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#define likely(_c) (_c)
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#define unlikely(_c) (_c)
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#endif
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#else /* !_XLC */
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#ifndef likely
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#define likely(_c) __builtin_expect((_c), 1)
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#define unlikely(_c) __builtin_expect((_c), 0)
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#endif
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#endif
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/**
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** Debug controls. Set -DNDEBUG to
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** disable both panic and assert.
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*/
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#include <assert.h>
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#define _spe_cache_panic_(c) assert(c)
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#ifdef SPE_CACHE_DBG
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#define _spe_cache_assert_(c) assert(c)
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#else
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#define _spe_cache_assert_(c) /* No-op. */
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#endif
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#define _spe_cacheline_byte_offset_(ea) \
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((ea) & SPE_CACHELINE_MASK)
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#define _spe_cacheline_byte_offset_x4(ea) \
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spu_and ((ea), SPE_CACHELINE_MASK)
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#endif
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static __inline vector unsigned int _load_vec_uint4(unsigned int ui1, unsigned int ui2, unsigned int ui3, unsigned int ui4)
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{
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vector unsigned int result;
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vector unsigned int iv1, iv2, iv3, iv4;
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vector unsigned char shuffle = VEC_LITERAL(vector unsigned char,
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0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80);
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iv1 = spu_promote(ui1, 0);
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iv2 = spu_promote(ui2, 0);
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iv3 = spu_promote(ui3, 0);
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iv4 = spu_promote(ui4, 0);
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result = spu_or(spu_shuffle(iv1, iv2, shuffle), spu_shuffle(iv3, iv4, spu_rlqwbyte(shuffle, 8)));
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return (result);
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}
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static __inline vector unsigned int _pack_vec_uint4(vector unsigned int ui1, vector unsigned int ui2, vector unsigned int ui3, vector unsigned int ui4)
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{
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vector unsigned int result;
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vector unsigned char shuffle = VEC_LITERAL(vector unsigned char,
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0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80);
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result = spu_or(spu_shuffle(ui1, ui2, shuffle), spu_shuffle(ui3, ui4, spu_rlqwbyte(shuffle, 8)));
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return (result);
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}
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/* --------------------------------------------------------------- */
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/* PLEASE DO NOT MODIFY THIS SECTION */
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/* This prolog section is automatically generated. */
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/* */
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/* (C) Copyright 2001,2006, */
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/* International Business Machines Corporation, */
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/* */
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/* All Rights Reserved. */
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/* --------------------------------------------------------------- */
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/* PROLOG END TAG zYx */
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/* spe_cache_defs.h
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*
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* Copyright (C) 2005 IBM Corp.
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*
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* Internal definitions for software managed cache.
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*/
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#ifndef __SPE_CACHE_DEFS_H__
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#define __SPE_CACHE_DEFS_H__
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/**
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** Defn's for number of cache sets.
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** Default is 64 sets.
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*/
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#if (SPE_CACHE_NSETS==1024)
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#define SPE_CACHE_NSETS_SHIFT 10
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#elif (SPE_CACHE_NSETS==512)
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#define SPE_CACHE_NSETS_SHIFT 9
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#elif (SPE_CACHE_NSETS==256)
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#define SPE_CACHE_NSETS_SHIFT 8
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#elif (SPE_CACHE_NSETS==128)
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#define SPE_CACHE_NSETS_SHIFT 7
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#elif (SPE_CACHE_NSETS==64)
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#define SPE_CACHE_NSETS_SHIFT 6
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#elif (SPE_CACHE_NSETS==32)
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#define SPE_CACHE_NSETS_SHIFT 5
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#elif (SPE_CACHE_NSETS==16)
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#define SPE_CACHE_NSETS_SHIFT 4
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#elif (SPE_CACHE_NSETS==8)
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#define SPE_CACHE_NSETS_SHIFT 3
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#elif (SPE_CACHE_NSETS==4)
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#define SPE_CACHE_NSETS_SHIFT 2
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#elif (SPE_CACHE_NSETS==2)
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#define SPE_CACHE_NSETS_SHIFT 1
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#else
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#undef SPE_CACHE_NSETS
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#define SPE_CACHE_NSETS 64
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#define SPE_CACHE_NSETS_SHIFT 6
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#endif
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/**
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** Defn's for cachline size (bytes).
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** Default is 128 bytes.
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*/
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#if (SPE_CACHELINE_SIZE==512)
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#define SPE_CACHELINE_SHIFT 9
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#elif (SPE_CACHELINE_SIZE==256)
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#define SPE_CACHELINE_SHIFT 8
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#elif (SPE_CACHELINE_SIZE==128)
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#define SPE_CACHELINE_SHIFT 7
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#elif (SPE_CACHELINE_SIZE==64)
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#define SPE_CACHELINE_SHIFT 6
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#elif (SPE_CACHELINE_SIZE==32)
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#define SPE_CACHELINE_SHIFT 5
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#else
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#undef SPE_CACHELINE_SIZE
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#define SPE_CACHELINE_SIZE 128
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#define SPE_CACHELINE_SHIFT 7
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#endif
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/**
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** Defn's derived from above settings.
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*/
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#define SPE_CACHE_NSETS_MASK (SPE_CACHE_NSETS - 1)
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#define SPE_CACHELINE_MASK (SPE_CACHELINE_SIZE - 1)
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/**
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** Defn's for managing cacheline state.
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*/
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#define SPE_CACHELINE_DIRTY 0x1
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#define SPE_CACHELINE_LOCKED 0x2
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#define SPE_CACHELINE_STATE_MASK (SPE_CACHELINE_DIRTY | SPE_CACHELINE_LOCKED)
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#ifdef _XLC
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/**
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* FIXME: For now disable manual branch hints
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* on XLC due to performance degradation.
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*/
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#ifndef likely
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#define likely(_c) (_c)
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#define unlikely(_c) (_c)
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#endif
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#else /* !_XLC */
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#ifndef likely
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#define likely(_c) __builtin_expect((_c), 1)
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#define unlikely(_c) __builtin_expect((_c), 0)
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#endif
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#endif
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/**
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** Debug controls. Set -DNDEBUG to
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** disable both panic and assert.
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*/
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#include <assert.h>
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#define _spe_cache_panic_(c) assert(c)
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#ifdef SPE_CACHE_DBG
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#define _spe_cache_assert_(c) assert(c)
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#else
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#define _spe_cache_assert_(c) /* No-op. */
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#endif
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#define _spe_cacheline_byte_offset_(ea) \
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((ea) & SPE_CACHELINE_MASK)
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#define _spe_cacheline_byte_offset_x4(ea) \
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spu_and ((ea), SPE_CACHELINE_MASK)
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#endif
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static __inline vector unsigned int _load_vec_uint4(unsigned int ui1, unsigned int ui2, unsigned int ui3, unsigned int ui4)
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{
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vector unsigned int result;
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vector unsigned int iv1, iv2, iv3, iv4;
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vector unsigned char shuffle = VEC_LITERAL(vector unsigned char,
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0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80);
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iv1 = spu_promote(ui1, 0);
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iv2 = spu_promote(ui2, 0);
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iv3 = spu_promote(ui3, 0);
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iv4 = spu_promote(ui4, 0);
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result = spu_or(spu_shuffle(iv1, iv2, shuffle), spu_shuffle(iv3, iv4, spu_rlqwbyte(shuffle, 8)));
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return (result);
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}
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static __inline vector unsigned int _pack_vec_uint4(vector unsigned int ui1, vector unsigned int ui2, vector unsigned int ui3, vector unsigned int ui4)
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{
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vector unsigned int result;
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vector unsigned char shuffle = VEC_LITERAL(vector unsigned char,
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0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80);
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result = spu_or(spu_shuffle(ui1, ui2, shuffle), spu_shuffle(ui3, ui4, spu_rlqwbyte(shuffle, 8)));
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return (result);
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}
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