Added IBM Cell SDK 2.x software_cache to Bullet/Extras. There is an option to enable it for the BulletMultiThreaded Cell version.
See USE_SOFTWARE_CACHE in Bullet\src\BulletMultiThreaded\SpuNarrowPhaseCollisionTask\SpuGatheringCollisionTask.cpp It improves the Bullet midphase collision detection (triangle/vertex fetch) The license is CommonPublicLicense-1.0, see included license docs.
This commit is contained in:
erwin.coumans
153
Extras/software_cache/cache/include/nway-opt.h
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153
Extras/software_cache/cache/include/nway-opt.h
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/* --------------------------------------------------------------- */
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/* PLEASE DO NOT MODIFY THIS SECTION */
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/* This prolog section is automatically generated. */
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/* */
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/* (C) Copyright 2001,2006, */
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/* International Business Machines Corporation, */
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/* */
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/* All Rights Reserved. */
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/* --------------------------------------------------------------- */
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/* PROLOG END TAG zYx */
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/* nway-opt.h
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*
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* Copyright (C) 2006 IBM Corp.
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*
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* "Optimized" lookup operations for n-way set associative
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* software managed cache.
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*/
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#include <spu_intrinsics.h>
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#ifndef __SPE_CACHE_NWAY_OPT_H_
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#define __SPE_CACHE_NWAY_OPT_H_
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/* __spe_cache_rd
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* Look up and return data from the cache. If the data
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* is not currently in cache then transfer it from main
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* storage.
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*
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* This code uses a conditional branch to the cache miss
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* handler in the event that the requested data is not
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* in the cache. A branch hint is used to avoid paying
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* the branch stall penalty.
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*/
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#define __spe_cache_rd(type, ea) \
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({ \
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int set, idx, lnum, byte; \
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type ret; \
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_spe_cache_nway_lookup_(ea, set, idx); \
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if (unlikely(idx < 0)) { \
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idx = _spe_cache_miss_(ea, set, -1); \
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spu_writech(22, SPE_CACHE_SET_TAGMASK(set)); \
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spu_mfcstat(MFC_TAG_UPDATE_ALL); \
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} \
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lnum = _spe_cacheline_num_(set, idx); \
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byte = _spe_cacheline_byte_offset_(ea); \
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ret = *((type *) (&spe_cache_mem[lnum + byte])); \
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ret; \
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})
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/**
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* __spe_cache_rd_x4
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* Fetch four data elements from the cache.
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*
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* This code uses one conditional branch in
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* the event that any of the four elements
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* are missing.
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*
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* On a miss, light weight locking is used to
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* avoid casting out entries that were found.
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* Further, we wait just once for the transfers,
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* allowing for parallel [rather than serial]
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* transfers.
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*/
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#define __spe_cache_rd_x4(type, ea_x4) \
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({ \
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vector unsigned int missing; \
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unsigned int ms; \
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vector unsigned int cindex; \
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unsigned int d0, d1, d2, d3; \
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vector unsigned int s_x4; \
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vector signed int i_x4; \
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vector unsigned int ibyte, iline; \
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vector unsigned int ret; \
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unsigned int idx0, idx1, idx2, idx3; \
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\
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_spe_cache_nway_lookup_x4(ea_x4, s_x4, i_x4); \
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missing = spu_rlmask ((vector unsigned int)i_x4, -8); \
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ms = spu_extract (spu_gather (missing), 0); \
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\
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ibyte = _spe_cacheline_byte_offset_x4(ea_x4); \
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\
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iline = _spe_cacheline_num_x4(s_x4, \
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(vector unsigned int)i_x4); \
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\
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cindex = spu_add (iline, ibyte); \
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\
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idx0 = spu_extract (cindex, 0); \
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idx1 = spu_extract (cindex, 1); \
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idx2 = spu_extract (cindex, 2); \
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idx3 = spu_extract (cindex, 3); \
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\
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d0 = *((type *) (&spe_cache_mem[idx0])); \
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d1 = *((type *) (&spe_cache_mem[idx1])); \
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d2 = *((type *) (&spe_cache_mem[idx2])); \
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d3 = *((type *) (&spe_cache_mem[idx3])); \
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\
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ret = _load_vec_uint4 (d0, d1, d2, d3); \
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\
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if (unlikely(ms)) { \
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int b0 = spu_extract (ibyte, 0); \
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int b1 = spu_extract (ibyte, 1); \
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int b2 = spu_extract (ibyte, 2); \
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int b3 = spu_extract (ibyte, 3); \
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int lnum0; \
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int lnum1; \
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int lnum2; \
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int lnum3; \
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int s0 = spu_extract (s_x4, 0); \
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int s1 = spu_extract (s_x4, 1); \
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int s2 = spu_extract (s_x4, 2); \
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int s3 = spu_extract (s_x4, 3); \
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int i0 = spu_extract (i_x4, 0); \
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int i1 = spu_extract (i_x4, 1); \
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int i2 = spu_extract (i_x4, 2); \
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int i3 = spu_extract (i_x4, 3); \
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unsigned int ea0 = spu_extract(ea_x4, 0); \
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unsigned int ea1 = spu_extract(ea_x4, 1); \
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unsigned int ea2 = spu_extract(ea_x4, 2); \
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unsigned int ea3 = spu_extract(ea_x4, 3); \
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int avail = -1; \
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\
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avail &= ~(((i0 < 0) ? 0 : (1 << i0)) | \
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((i1 < 0) ? 0 : (1 << i1)) | \
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((i2 < 0) ? 0 : (1 << i2)) | \
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((i3 < 0) ? 0 : (1 << i3))); \
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\
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i0 = _spe_cache_miss_(ea0, s0, avail); \
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avail &= ~(1 << i0); \
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i1 = _spe_cache_miss_(ea1, s1, avail); \
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avail &= ~(1 << i1); \
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i2 = _spe_cache_miss_(ea2, s2, avail); \
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avail &= ~(1 << i2); \
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i3 = _spe_cache_miss_(ea3, s3, avail); \
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\
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lnum0 = _spe_cacheline_num_(s0, i0); \
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lnum1 = _spe_cacheline_num_(s1, i1); \
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lnum2 = _spe_cacheline_num_(s2, i2); \
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lnum3 = _spe_cacheline_num_(s3, i3); \
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\
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spu_writech(22, SPE_CACHE_SET_TAGMASK(set)); \
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spu_mfcstat(MFC_TAG_UPDATE_ALL); \
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\
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d0 = *((type *) (&spe_cache_mem[lnum0 + b0])); \
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d1 = *((type *) (&spe_cache_mem[lnum1 + b1])); \
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d2 = *((type *) (&spe_cache_mem[lnum2 + b2])); \
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d3 = *((type *) (&spe_cache_mem[lnum3 + b3])); \
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\
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ret = _load_vec_uint4 (d0, d1, d2, d3); \
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} \
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ret; \
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})
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#endif /* _SPE_CACHE_NWAY_OPT_H_ */
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