dc8692ba94
See USE_SOFTWARE_CACHE in Bullet\src\BulletMultiThreaded\SpuNarrowPhaseCollisionTask\SpuGatheringCollisionTask.cpp It improves the Bullet midphase collision detection (triangle/vertex fetch) The license is CommonPublicLicense-1.0, see included license docs.
106 lines
3.9 KiB
C
106 lines
3.9 KiB
C
/* --------------------------------------------------------------- */
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/* PLEASE DO NOT MODIFY THIS SECTION */
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/* This prolog section is automatically generated. */
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/* */
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/* (C) Copyright 2001,2006, */
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/* International Business Machines Corporation, */
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/* */
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/* All Rights Reserved. */
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/* --------------------------------------------------------------- */
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/* PROLOG END TAG zYx */
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/* nway.h
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*
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* Copyright (C) 2005 IBM Corp.
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*
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* Support for n-way set associative software
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* managed cache. The 4-way associative cache
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* is the only interface exposed currently.
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*/
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#ifndef __SPE_CACHE_NWAY_H_
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#define __SPE_CACHE_NWAY_H_
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/**
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** Defn's for n-way set associativity.
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** Default is 4-way.
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*/
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#define SPE_CACHE_NWAY 4
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#define SPE_CACHE_NWAY_SHIFT 2
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#define SPE_CACHE_NWAY_MASK (SPE_CACHE_NWAY - 1)
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#define SPE_CACHE_NENTRIES (SPE_CACHE_NWAY * SPE_CACHE_NSETS)
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#define SPE_CACHE_MEM_SIZE (SPE_CACHE_NENTRIES * SPE_CACHELINE_SIZE)
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#define _spe_cache_set_num_(ea) \
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({ \
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unsigned int ead, eadm, ret; \
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ead = ((ea) >> SPE_CACHELINE_SHIFT); \
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eadm = ((ea) >> (SPE_CACHELINE_SHIFT+2)); \
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ret = (ead ^ eadm) & SPE_CACHE_NSETS_MASK; \
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ret; \
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})
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#define _spe_cache_set_num_x4(ea_x4) \
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({ \
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vector unsigned int tmp0; \
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vector unsigned int tmp1; \
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tmp0 = spu_rlmask (ea_x4, -SPE_CACHELINE_SHIFT); \
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tmp1 = spu_rlmask (ea_x4, -(SPE_CACHELINE_SHIFT+1)); \
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spu_and (spu_xor (tmp0, tmp1), SPE_CACHE_NSETS_MASK); \
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})
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#define _spe_cache_idx_num_x4(found) \
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spu_sub((unsigned int) 31, spu_cntlz(found))
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#define _spe_cache_idx_num_(found) \
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spu_extract(spu_sub((unsigned int) 31, spu_cntlz(found)), 0)
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#define _spe_cacheline_num_(set, idx) \
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(((set << SPE_CACHE_NWAY_SHIFT) + idx) << SPE_CACHELINE_SHIFT)
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#define _spe_cacheline_num_x4(set, idx) \
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spu_sl (spu_add (spu_sl (set, SPE_CACHE_NWAY_SHIFT), idx), SPE_CACHELINE_SHIFT)
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#define _spe_cacheline_is_dirty_(set, idx) \
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(spe_cache_dir[set][SPE_CACHE_NWAY_MASK-(idx)] & SPE_CACHELINE_DIRTY)
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#define _spe_cacheline_is_locked_(set, idx) \
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(spe_cache_dir[set][SPE_CACHE_NWAY_MASK-(idx)] & SPE_CACHELINE_LOCKED)
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#define _spe_lock_cacheline_(set, idx) \
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spe_cache_dir[set][SPE_CACHE_NWAY_MASK-(idx)] |= SPE_CACHELINE_LOCKED
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#define _spe_unlock_cacheline_(set, idx) \
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spe_cache_dir[set][SPE_CACHE_NWAY_MASK-(idx)] &= ~SPE_CACHELINE_LOCKED
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/**
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* spe_cache_dir
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* This is the n-way set associative cache
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* directory. Entries are either zero (unused)
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* or non-zero (used).
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*
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* State for one additional (dummy) set is
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* allocated to improve efficiency of cache
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* line locking.
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* volatile seems not to be necessary here, the SCE toolchain guarantees a barrier after dma transfer
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*/
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static unsigned int spe_cache_dir[SPE_CACHE_NSETS+1][SPE_CACHE_NWAY]
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__attribute__ ((aligned(16)));
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/**
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* spe_cache_mem
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* A contiguous set of cachelines in LS memory,
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* one line for each entry in the cache.
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* volatile seems not to be necessary here, the SCE toolchain guarantees a barrier after dma transfer
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*/
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static char spe_cache_mem[SPE_CACHE_MEM_SIZE]
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__attribute__ ((aligned(128)));
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#include "nway-lookup.h"
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#include "nway-replace.h"
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#include "nway-miss.h"
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#include "nway-opt.h"
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#endif
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