dc8692ba94
See USE_SOFTWARE_CACHE in Bullet\src\BulletMultiThreaded\SpuNarrowPhaseCollisionTask\SpuGatheringCollisionTask.cpp It improves the Bullet midphase collision detection (triangle/vertex fetch) The license is CommonPublicLicense-1.0, see included license docs.
246 lines
11 KiB
C
246 lines
11 KiB
C
/* @(#)17 1.4 src/include/cbe_mfc.h, sw.includes, sdk_pub 10/11/05 16:00:25 */
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/* -------------------------------------------------------------- */
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/* (C) Copyright 2001,2005, */
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/* International Business Machines Corporation, */
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/* Sony Computer Entertainment Incorporated, */
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/* Toshiba Corporation. */
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/* */
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/* All Rights Reserved. */
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/* -------------------------------------------------------------- */
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/* PROLOG END TAG zYx */
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#ifndef _CBEA_MFC_H_
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#define _CBEA_MFC_H_
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/* This header file contains various definitions related to the Memory Flow
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* Controller (MFC) portion of the Cell Broadband Engine Architecture (CBEA).
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*/
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/**************************************/
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/* MFC DMA Command Opcode Definitions */
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/**************************************/
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/****************************************************************************/
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/* MFC DMA Command flags which identify classes of operations. */
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/****************************************************************************/
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/* Note: These flags may be used in conjunction with the base command types
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* (i.e. MFC_PUT_CMD, MFC_PUTR_CMD, MFC_GET_CMD, and MFC_SNDSIG_CMD)
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* to construct the various command permutations.
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*/
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#define MFC_BARRIER_ENABLE 0x01
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#define MFC_FENCE_ENABLE 0x02
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#define MFC_LIST_ENABLE 0x04 /* SPU Only */
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#define MFC_START_ENABLE 0x08 /* proxy Only */
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#define MFC_RESULT_ENABLE 0x10
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/****************************************************************************/
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/* MFC DMA Put Commands */
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/****************************************************************************/
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#define MFC_PUT_CMD 0x20
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#define MFC_PUTS_CMD 0x28 /* proxy Only */
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#define MFC_PUTR_CMD 0x30
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#define MFC_PUTF_CMD 0x22
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#define MFC_PUTB_CMD 0x21
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#define MFC_PUTFS_CMD 0x2A /* proxy Only */
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#define MFC_PUTBS_CMD 0x29 /* proxy Only */
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#define MFC_PUTRF_CMD 0x32
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#define MFC_PUTRB_CMD 0x31
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#define MFC_PUTL_CMD 0x24 /* SPU Only */
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#define MFC_PUTRL_CMD 0x34 /* SPU Only */
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#define MFC_PUTLF_CMD 0x26 /* SPU Only */
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#define MFC_PUTLB_CMD 0x25 /* SPU Only */
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#define MFC_PUTRLF_CMD 0x36 /* SPU Only */
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#define MFC_PUTRLB_CMD 0x35 /* SPU Only */
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/****************************************************************************/
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/* MFC DMA Get Commands */
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/****************************************************************************/
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#define MFC_GET_CMD 0x40
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#define MFC_GETS_CMD 0x48 /* proxy Only */
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#define MFC_GETF_CMD 0x42
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#define MFC_GETB_CMD 0x41
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#define MFC_GETFS_CMD 0x4A /* proxy Only */
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#define MFC_GETBS_CMD 0x49 /* proxy Only */
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#define MFC_GETL_CMD 0x44 /* SPU Only */
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#define MFC_GETLF_CMD 0x46 /* SPU Only */
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#define MFC_GETLB_CMD 0x45 /* SPU Only */
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/****************************************************************************/
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/* MFC DMA Storage Control Commands */
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/****************************************************************************/
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/* Note: These are only supported on implementations with a SL1 cache
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* They are no-ops on the initial (CBE) implementation.
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*/
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#define MFC_SDCRT_CMD 0x80
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#define MFC_SDCRTST_CMD 0x81
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#define MFC_SDCRZ_CMD 0x89
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#define MFC_SDCRS_CMD 0x8D
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#define MFC_SDCRF_CMD 0x8F
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/****************************************************************************/
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/* MFC Synchronization Commands */
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/****************************************************************************/
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#define MFC_GETLLAR_CMD 0xD0 /* SPU Only */
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#define MFC_PUTLLC_CMD 0xB4 /* SPU Only */
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#define MFC_PUTLLUC_CMD 0xB0 /* SPU Only */
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#define MFC_PUTQLLUC_CMD 0xB8 /* SPU Only */
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#define MFC_SNDSIG_CMD 0xA0
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#define MFC_SNDSIGB_CMD 0xA1
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#define MFC_SNDSIGF_CMD 0xA2
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#define MFC_BARRIER_CMD 0xC0
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#define MFC_EIEIO_CMD 0xC8
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#define MFC_SYNC_CMD 0xCC
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/****************************************************************************/
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/* Definitions for constructing a 32-bit command word including the transfer
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* and replacement class id and the command opcode.
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*/
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/****************************************************************************/
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#define MFC_TCLASS(_tid) ((_tid) << 24)
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#define MFC_RCLASS(_rid) ((_rid) << 16)
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#define MFC_CMD_WORD(_tid, _rid, _cmd) (MFC_TCLASS(_tid) | MFC_RCLASS(_rid) | (_cmd))
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/****************************************************************************/
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/* Definitions for constructing a 64-bit command word including the size, tag,
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* transfer and replacement class id and the command opcode.
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*/
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/****************************************************************************/
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#define MFC_SIZE(_size) ((unsigned long long)(_size) << 48)
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#define MFC_TAG(_tag_id) ((unsigned long long)(_tag_id) << 32)
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#define MFC_TR_CMD(_trcmd) ((unsigned long long)(_trcmd))
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#define MFC_CMD_DWORD(_size, _tag_id, _trcmd) (MFC_SIZE(_size) | MFC_TAG(_tag_id) | MFC_TR_CMD(_trcmd))
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/****************************************************************************/
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/* Mask definitions for obtaining DMA commands and class ids from packed words.
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*/
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/****************************************************************************/
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#define MFC_CMD_MASK 0x0000FFFF
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#define MFC_CLASS_MASK 0x000000FF
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/****************************************************************************/
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/* DMA max/min size definitions. */
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/****************************************************************************/
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#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
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#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
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#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
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#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
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#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
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#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
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#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
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#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
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/****************************************************************************/
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/* Mask definition for checking proper address alignment. */
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/****************************************************************************/
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#define MFC_ADDR_MATCH_MASK 0xF
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#define MFC_BEST_ADDR_ALIGNMENT 0x80
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/****************************************************************************/
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/* Definitions related to the Proxy DMA Command Status register (DMA_CMDStatus).
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*/
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/****************************************************************************/
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#define MFC_PROXY_DMA_CMD_ENQUEUE_SUCCESSFUL 0x00
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#define MFC_PROXY_DMA_CMD_SEQUENCE_ERROR 0x01
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#define MFC_PROXY_DMA_QUEUE_FULL 0x02
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/****************************************************************************/
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/* Definitions related to the DMA Queue Status register (DMA_QStatus). */
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/****************************************************************************/
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#define MFC_PROXY_MAX_QUEUE_SPACE 0x08
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#define MFC_PROXY_DMA_Q_EMPTY 0x80000000
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#define MFC_PROXY_DMA_Q_FREE_SPACE_MASK 0x0000FFFF
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#define MFC_SPU_MAX_QUEUE_SPACE 0x10
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/****************************************************************************/
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/* Definitions related to the Proxy Tag-Group Query-Type register
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* (Prxy_QueryType).
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*/
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/****************************************************************************/
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#define MFC_PROXY_DMA_QUERYTYPE_ANY 0x1
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#define MFC_PROXY_DMA_QUERYTYPE_ALL 0x2
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/****************************************************************************/
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/* Definitions related to the Proxy Tag-Group Query-Mask (Prxy_QueryMask)
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* and PU Tag Status (DMA_TagStatus) registers.
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*
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* NOTE: The only use the bottom 5 bits of the tag id value passed to insure
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* a valid tag id is used.
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*/
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/****************************************************************************/
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#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
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/****************************************************************************/
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/* Definitions related to the Mailbox Status register (SPU_Mbox_Stat) and the
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* depths of the outbound Mailbox Register (SPU_OutMbox), the outbound
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* interrupting Mailbox Register (SPU_OutIntrMbox), and the inbound Mailbox
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* Register (SPU_In_Mbox).
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*/
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/****************************************************************************/
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#define MFC_SPU_OUT_MBOX_COUNT_STATUS_MASK 0x000000FF
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#define MFC_SPU_OUT_MBOX_COUNT_STATUS_SHIFT 0x0
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#define MFC_SPU_IN_MBOX_COUNT_STATUS_MASK 0x0000FF00
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#define MFC_SPU_IN_MBOX_COUNT_STATUS_SHIFT 0x8
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#define MFC_SPU_OUT_INTR_MBOX_COUNT_STATUS_MASK 0x00FF0000
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#define MFC_SPU_OUT_INTR_MBOX_COUNT_STATUS_SHIFT 0x10
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/****************************************************************************/
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/* Definitions related to the SPC Multi Source Syncronization register
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* (MFC_MSSync).
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*/
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/****************************************************************************/
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#define MFC_SPC_MSS_STATUS_MASK 0x1
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#define MFC_SPC_MSS_COMPLETE 0x0
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#define MFC_SPC_MSS_NOT_COMPLETE 0x1
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/*******************************************
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* Channel Defines
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*******************************************/
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/* Events Defines for channels:
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* 0 (SPU_RdEventStat),
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* 1 (SPU_WrEventMask), and
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* 2 (SPU_WrEventAck).
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*/
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#define MFC_TAG_STATUS_UPDATE_EVENT 0x00000001
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#define MFC_LIST_STALL_NOTIFY_EVENT 0x00000002
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#define MFC_COMMAND_QUEUE_AVAILABLE_EVENT 0x00000008
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#define MFC_IN_MBOX_AVAILABLE_EVENT 0x00000010
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#define MFC_DECREMENTER_EVENT 0x00000020
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#define MFC_OUT_INTR_MBOX_AVAILABLE_EVENT 0x00000040
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#define MFC_OUT_MBOX_AVAILABLE_EVENT 0x00000080
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#define MFC_SIGNAL_NOTIFY_2_EVENT 0x00000100
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#define MFC_SIGNAL_NOTIFY_1_EVENT 0x00000200
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#define MFC_LLR_LOST_EVENT 0x00000400
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#define MFC_PRIV_ATTN_EVENT 0x00000800
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#define MFC_MULTI_SRC_SYNC_EVENT 0x00001000
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/* Tag Status Update defines for channel 23 (MFC_WrTagUpdate)
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*/
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#define MFC_TAG_UPDATE_IMMEDIATE 0x0
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#define MFC_TAG_UPDATE_ANY 0x1
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#define MFC_TAG_UPDATE_ALL 0x2
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/* Atomic Command Status defines for channel 27 (MFC_RdAtomicStat)
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*/
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#define MFC_PUTLLC_STATUS 0x00000001
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#define MFC_PUTLLUC_STATUS 0x00000002
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#define MFC_GETLLAR_STATUS 0x00000004
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#endif /* _CBEA_MFC_H_ */
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